Current Issue : July - September Volume : 2013 Issue Number : 3 Articles : 5 Articles
This paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implementââ?¬â?on\r\na full-custom asynchronous FPGAââ?¬â?secured functions that need to be robust against side-channel attacks (SCAs). The paper\r\nbriefly describes the architecture of this FPGA that has been designed and prototyped in CMOS 65nm to target various styles\r\nof asynchronous logic including 2-phase and 4-phase communication protocols and 1-of-n data encoding. This programmable\r\narchitecture is designed to be electrically balanced in order to fit the security requirements. It allows fair comparisons between\r\ndifferent styles of asynchronous implementations. In order to illustrate the FPGA flexibility and security, a case study has been\r\nimplemented in 2-phase and 4-phase Quasi-Delay-Insensitive (QDI) logic....
In this paper, a configurable superimposed training (ST)/data-dependent ST (DDST) transmitter and architecture based on\r\narray processors (APs) for DDST channel estimation are presented. Both architectures, designed under full-hardware paradigm,\r\nwere described using Verilog HDL, targeted in Xilinx Virtex-5 and they were compared with existent approaches. The synthesis\r\nresults showed a FPGA slice consumption of 1% for the transmitter and 3% for the estimator with 160 and 115MHz operating\r\nfrequencies, respectively. The signal-to-quantization-noise ratio (SQNR) performance of the transmitter is about 82 dB to support\r\n4/16/64-QAM modulation. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator\r\nimplemented in hardware is practically the same as the one obtained with the floating-point golden model. The high performance\r\nand reduced hardware of the proposed architectures lead to the conclusion that the DDST concept can be applied in current\r\ncommunications standards....
This work presents the integration of several IPs to generate a system-on-chip (SoC) for digital television set-top box compliant to the SBTVD standard. Embedded consumer electronics for multimedia applications like video processing systems require large storage capacity and high bandwidth memory. Also, those systems are built from heterogeneous processing units, designed to perform specific tasks in order to maximize the overall system efficiency. A single off-chip memory is generally shared between the processing units to reduce power and save costs. The external memory access is one bottleneck when decoding high-definition video sequences in real time. In this work, a four-level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The use of the memory hierarchy in the system design is challenging because it impacts the system integration process and IP reuse in a collaborative design team. Practical strategies used to solve integration problems are discussed in this text. The SoC architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board....
Due to the fast changing wireless communication standards coupled with strict performance constraints, the demand for flexible\r\nyet high-performance architectures is increasing. To tackle the flexibility requirement, software-defined radio (SDR) is emerging\r\nas an obvious solution, where the underlying hardware implementation is tuned via software layers to the varied standards\r\ndepending on power-performance and quality requirements leading to adaptable, cognitive radio. In this paper, we conduct\r\na case study for representatives of two complexity classes of WCDMA channel estimation algorithms and explore the effect of\r\nflexibility on energy efficiency using different implementation options. Furthermore, we propose new design guidelines for both\r\nhighly specialized architectures and highly flexible architectures using high-level synthesis, to enable the required performance\r\nand flexibility to support multiple applications. Our experiments with various design points show that the resulting architectures\r\nmeet the performance constraints ofWCDMA and a wide range of options are offered for tuning such architectures depending on\r\npower/performance/area constraints of SDR....
Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different\r\nparts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been\r\nexecuted in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and theUnified Power Format\r\n(UPF). The purpose of this paper is to present an OSCI SystemC simulator with support to the power gating design. This simulator\r\nis an alternative to assist the functional verification accomplishment of systems modeled in RTL. The possibility of controlling the\r\nretention and isolation of power gated functional block (PGFB) is presented in this work, turning the simulations more stable and\r\naccurate. Two case studies are presented to demonstrate the new features of that simulator....
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